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authorBerke Güzel <wenekar1@gmail.com>2026-10-12 17:49:34 +0300
committerBerke Güzel <wenekar1@gmail.com>2026-10-12 17:49:34 +0300
commit4384435941b8c7658856b381d071aee2e0035e89 (patch)
tree5ece99c3dd1decb8ec3fd404c0ece2b5865a552a /src/isa.c
term: move the term core to subprojects/term
The core now builds, tests, and benchmarks alone, as a Meson subproject with no dependency on the main tree. - include/term/ holds term.h and the header-only unicode/. src/ holds the core and its private headers. The main tree gets only include/term through term_dep, so it cannot reach a private header. - The term tests, the term benchmarks, the Kitty parser suite, and tools/amalgamate.py and tools/generate_unicode.py move with it. The tests run as term:<name>. - The main build passes its -march (arch_flag) and b_ndebug to the subproject. A directory configured before this commit needs meson configure -Dterm:arch_flag=-march=... once. - The term tests compile with -UNDEBUG. They do work inside assert. - The subproject exports term_test_dep with term_api.h, for the main tree's render, thumbnail, color, and selection tests. - The Kitty bridge used struct vector2i and has not compiled since the public API redesign. It builds again. 2 of its 14 tests fail: REP after a tab, and a cursor report after a resize. - dirgraph.py drops the term and unicode layers. Its self-test uses pty. - The symbols test ignores the __odr_asan symbols that ASan adds. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Diffstat (limited to 'src/isa.c')
-rw-r--r--src/isa.c78
1 files changed, 78 insertions, 0 deletions
diff --git a/src/isa.c b/src/isa.c
new file mode 100644
index 0000000..1fe1517
--- /dev/null
+++ b/src/isa.c
@@ -0,0 +1,78 @@
+/*
+ * The instruction set level. See simd.h. The level is picked once, before
+ * the first terminal exists, so every call in a process uses the same
+ * kernels.
+ */
+#include "term.h"
+#include "simd.h"
+
+#include <stdatomic.h>
+#include <stdlib.h>
+#include <string.h>
+
+int term_isa_level;
+static atomic_int isa_state;
+
+static const char *const level_names[] = { "base", "avx2", "avx512" };
+
+#if defined(TERM_ISA_RUNTIME)
+/* The AVX-512 kernels also need VBMI and VBMI2. Every CPU with VBMI except
+ * Cannon Lake has VBMI2. */
+static int cpu_level(void)
+{
+ __builtin_cpu_init();
+ if (__builtin_cpu_supports("x86-64-v4") && __builtin_cpu_supports("avx512vbmi") &&
+ __builtin_cpu_supports("avx512vbmi2"))
+ return TERM_ISA_AVX512;
+ if (__builtin_cpu_supports("x86-64-v3"))
+ return TERM_ISA_AVX2;
+ return TERM_ISA_BASE;
+}
+#else
+static int cpu_level(void)
+{
+ return TERM_ISA_FLOOR;
+}
+#endif
+
+static int pick_level(void)
+{
+ int level = cpu_level();
+ /* TERM_HEADLESS_ISA can only lower the level, never below the floor the
+ * compiler flags fix. */
+ const char *want = getenv("TERM_HEADLESS_ISA");
+ for (int i = TERM_ISA_FLOOR; want && i < level; i++)
+ if (!strcmp(want, level_names[i]))
+ level = i;
+ return level;
+}
+
+/* The first caller picks the level. A second caller waits until it is set. */
+void term_isa_init(void)
+{
+ if (atomic_load_explicit(&isa_state, memory_order_acquire) == 2)
+ return;
+ int expected = 0;
+ if (atomic_compare_exchange_strong(&isa_state, &expected, 1)) {
+ term_isa_level = pick_level();
+ atomic_store_explicit(&isa_state, 2, memory_order_release);
+ return;
+ }
+ while (atomic_load_explicit(&isa_state, memory_order_acquire) != 2)
+ term_cpu_relax();
+}
+
+const char *term_isa(void)
+{
+ term_isa_init();
+#if defined(__aarch64__)
+ return "neon";
+#else
+ int level = TERM_ISA_FLOOR;
+ if (term_use_avx2())
+ level = TERM_ISA_AVX2;
+ if (term_use_avx512())
+ level = TERM_ISA_AVX512;
+ return level_names[level];
+#endif
+}